Silicon chip manufacturers like Intel and TSMC are constantly outdoing themselves to make ever smaller features, but they are getting closer to the physical limits of silicon itself.
“We already have very, very high density in silicon-based architectures where silicon performance degrades sharply,” said Ki Seok Kim, a scientist working at the MIT’s Research Laboratory of Electronics.
One way around this problem is to replace silicon with graphene-like 2D materials that maintain their semiconducting properties even at a single-atom scale. Another way is building 3D chips, which squeeze more transistors into the same area without making transistors smaller. Kim’s team did both, building a 3D chip out of vertically stacked 2D semiconductors.
Source : https://arstechnica.com/science/2025/01/making-a-3d-stack-of-transistors-made-from-2d-materials/
